Why does a partial autorouter that stops at 87%–97% completion still cost hardware engineers days of manual rework?
Because the last 3%–13% of unrouted airwires and design-rule clearance errors occur inside dense BGA/QFN escape corridors where earlier tracks have already boxed in the remaining pins.
Calligraphy EDA enforces a strict fail-closed commercial gate (NO_PARTIAL_SALES = True): you never pay for a board with even a single unconnected net or native KiCad copper DRC violation.
| Board / Architecture | Layers & Density | Net Completion | Native KiCad Copper DRC | Engineering Capabilities Verified |
|---|---|---|---|---|
| 8-Layer i.MX8M Mini SOM (`royalblue54l`) | 8L HDI • 746 Pads | 100.0% (0 Opens) | 0 Violations | High-Density BGA Escape Allocation & Global Multi-Layer Congestion Balancing |
| Zynq-7000 SoC + DDR3 Memory (`bga196`) | 4L Commercial • 512 Pads | 100.0% (0 Opens) | 0 Violations | Impedance-Controlled Differential Pair Coupling & Phase-Matched Flight-Time Tuning |
| STM32H7 Dual-Port Industrial EtherCAT | 4L Industrial • 468 Pads | 100.0% (0 Opens) | 0 Violations | 3D Return-Path Continuity, Loop-Inductance Control & 3D Nodal (G*V=I) Drop Audit |
| ColdFire V2 FPGA Evaluation Carrier | 4L Mixed-Signal • 620 Pads | 100.0% (0 Opens) | 0 Violations | Fine-Pitch QFP Escape, Design-Rule Clearance Verification & Snowman Teardrop Fillets |
| 10 PCBench Tier D Torture Boards (`d1`..`d20`) | 2L & 4L High-Congestion | 100.0% (0 Opens) | 0 Violations | 0.00000 mm Coordinate Drift Round-Trip across Specctra DSN, KiCad & Altium |
.kicad_pcb, .PcbDoc, .dsn, .ato, or .tsx board and inspect the 350-DPI Proof Loupe before paying a cent.